module lvds_top
(
input   					inclk,
input						pll_rst,
input						tx_vld,
input						tx_done,
input						ki,
input		[7:0]			tx_data,
output    				tx,

input						rx,
output					ko,
output   [7:0]       rx_data,
output					rx_data_en,
output					clk_10M ,
output               pll_locked



);






wire clk_100M,clk_400M;
wire   rst=!pll_locked;

trans_data   trans_data_inst  //transmit data
(

.rst			(rst),
.clk_10M		(clk_10M),
.clk_100M	(clk_100M),
.tx_vld		(tx_vld),
.tx_done		(tx_done),
.ki			(ki),
.tx_data		(tx_data),
.tx_out		(tx)

);



recv_data   recv_data_inst
(
.rst				(rst),
.clk_100M		(clk_100M),
.clk_400M		(clk_400M),
.rx				(rx),
.ko_r				(ko),
.rx_data_r		(rx_data),
.rx_data_en_r	(rx_data_en)



);




plltx_rx	plltx_rx_inst (
	.areset (pll_rst ),
	.inclk0 ( inclk),
	.c0 ( clk_10M ),
	.c1 ( clk_100M),
	.c2 ( clk_400M ),
	.locked ( pll_locked )
	);



endmodule
